// Verilog版测试激励文件HDB3proj_tb.v:
`timescale 10ns/10ns
module HDB3proj_tb();

  reg In_reset;
  reg In_clock;
  reg In_enable;
  
  wire E1_clock;
  wire V_code;
  wire BV_code;
  wire Out_code;
  
  wire [1:0] HDB3_code;
  wire [1:0] HDB3_wave;
  
  initial 
  begin
    In_reset=1'b1;
    In_clock=1'b0;
    In_enable=1'b0;
    #16	In_reset=1'b0;
    #16 In_reset=1'b1;
    #4		In_enable=1'b1;
    #384  	In_enable=1'b0;
    #624  	In_enable=1'b1;
    #4032	In_enable=1'b0;
    #336 	In_enable=1'b1;
    #720  	In_enable=1'b0; 
  end
  
  always #1 In_clock=~In_clock;
    
  HDB3proj DUT(
  .In_reset(In_reset),
  .In_clock(In_clock),
  .In_enable(In_enable),
  .E1_clock(E1_clock),
  .V_code(V_code),
  .BV_code(BV_code),
  .HDB3_code(HDB3_code),
  .HDB3_wave(HDB3_wave),
  .Out_code(Out_code)
  );
  
 endmodule